Semiconductor memory devices are commonly used in a variety of devices. Their most apparent use is in data processing systems, where they store programs and data. They also perform less obvious functions, such as I/O buffering and screen display control. In many of these applications, speed in writing to and reading from individual memory cells is a critical factor. However, systems designers are often forced to sacrifice speed to meet competing requirements of reduced size and cost.
Dynamic random access memory (DRAMs) are widely accepted memory devices because of their high density and low cost. Nonetheless, DRAMs do not always perform with the desired speed. Accordingly, shortening the time required to access individual memory cells in DRAMs is a significant and ongoing endeavor.
Besides shortening individual memory cell access times, designers have also sought to improve the efficiency of memory access cycles by eliminating repetitive specification of memory addresses. Accordingly, some DRAM's have alternate addressing modes such as page mode, static column mode, and nibble mode. DRAM's utilizing these addressing modes are described in Micron's MOS Data Book (1990/A), section 1, the disclosure of which is incorporated by reference. These methods of accessing memory cells nevertheless require a discrete access cycle for each memory cell which is read from or written to.
Most methods of memory access allow writing to only a single memory cell during each access cycle. However, a "flash write" mode has been used with some DRAMs to allow simultaneous writing of a single data bit to an entire row of memory cells. In a flash write cycle, only the address of a row within a two-dimensional memory array is specified. The single data bit is then written to every memory cell in the specified row of the memory array. Mitsubishi Data Book (1990) Section 4 (video memory), incorporated by reference, describes a DRAM which provides for flash write.
While flash write allows simultaneous writing to a significant group of memory cells, it is often impractical because, in many applications, it is somewhat rare to find an entire row which will be written to a single value. In contrast, an embodiment of the present invention allows addressing of an arbitrarily selected subset of memory cells within a row. Another embodiment of the invention allows addressing of multiple entire rows. These and other embodiments, described below, thus allow arbitrarily selected contiguous groups of memory cells to be addressed and written to a single logic value during a single write cycle. The time required to write to such a group of memory cells is, therefore, drastically reduced, resulting in a significant reduction in external circuit overhead. These advantages are obtained while maintaining compatibility with existing conventional DRAM circuits, so that write cycles directed to single memory cells may also be performed in the conventional manner.